COP1 010001 |
fmt 10110 |
ft |
fs |
fd |
PUU 101111 |
6 |
5 |
5 |
5 |
5 |
6 |
PUU.PS fd, fs, ft |
MIPS64, MIPS32 Release 2,, removed in Release 6 |
Pair Upper Upper |
Pair Upper Upper
To merge a pair of paired single values with realignment.
FPR[fd] = upper(FPR[fs]) || upper(FPR[ft])
A new paired-single value is formed by catenating the upper single of FPR fs (bits 63..32) and the upper single of
FPR ft (bits 63..32).
The move is non-arithmetic; it causes no IEEE 754 exceptions, and the FCSRCause and FCSRFlags fields are not modified.
The fields fs, ft, and fd must specify FPRs valid for operands of type PS. If the fields are not valid, the result is
UNPREDICTABLE.
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
This instruction has been removed in Release 6.
StoreFPR(fd, PS, ValueFPR(fs, PS)63..32 || ValueFPR(ft, PS)63..32)
Coprocessor Unusable, Reserved Instruction