Encoding:

MSA

011110

000

df

s5

ws

wd

I5

000111

6

3

2

5

5

5

6

Format:

CEQI.df 

Immediate Compare Equal

CEQI.B wd,ws,s5

MSA

Immediate Compare Equal

CEQI.H wd,ws,s5

MSA

Immediate Compare Equal

CEQI.W wd,ws,s5

MSA

Immediate Compare Equal

CEQI.D wd,ws,s5

MSA

Immediate Compare Equal

Purpose:

Immediate Compare Equal

Immediate to vector compare for equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] = s5)

Set all bits to 1 in wd elements if the corresponding ws element and the 5-bit signed immediate s5 are equal, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CEQI.B:
   t = (s54)3 || s54..0
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i = t
      WR[wd]8i+7..8i = c8
   endfor
CEQI.H:
   t = (s54)11 || s54..0
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i = t
      WR[wd]16i+15..16i = c16
   endfor
CEQI.W:
   t = (s54)27 || s54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i = t
      WR[wd]32i+31..32i = c32
   endfor
CEQI.D:
   t = (s54)59 || s54..0
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i = t
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.