Encoding:

Format:

SDXC1 fs, index(base)

Purpose:

Store Doubleword Indexed from Floating Point

To store a doubleword from an FPR to memory (GPR+GPR addressing).

Description:

 memory[GPR[base] + GPR[index]] = FPR[fs]

The 64-bit doubleword in FPR fs is stored in memory at the location specified by the aligned effective address. The contents of GPR index and GPR base are added to form the effective address.

Restrictions:

An Address Error exception occurs if EffectiveAddress_2..0 != 0 (not doubleword-aligned). Availability and Compatibility:

This instruction has been removed in Release 6.

Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required in

MIPS32 Release 2 and all subsequent versions of MIPS32. When required, these instructions are to be implemented if an FPU is present either in a 32-bit or 64-bit FPU or in a 32-bit or 64-bit FP Register Mode (FIRF64=0 or 1,

Status_FR=0 or 1).

Operation:

vAddr = GPR[base] + GPR[index]
if vAddr2..0 != 03 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation(vAddr, DATA, STORE)
datadoubleword = ValueFPR(fs, UNINTERPRETED_DOUBLEWORD)
StoreMemory(CCA, DOUBLEWORD, datadoubleword, pAddr, vAddr, DATA)
paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02)
StoreMemory(CCA, WORD, datadoubleword31..0, pAddr, vAddr, DATA)
paddr = paddr xor 0b100
StoreMemory(CCA, WORD, datadoubleword63..32, pAddr, vAddr+4, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Coprocessor Unusable, Address Error, Reserved Instruction, Watch.