Encoding:

Format:

SRLR.df 

SRLR.B wd,ws,wt

SRLR.H wd,ws,wt

SRLR.W wd,ws,wt

SRLR.D wd,ws,wt

Purpose:

Vector Shift Right Logical Rounded

Vector bit count shift right logical with rounding

Description:

wd[i] = ws[i] >>(rounded) wt[i]

The elements in vector ws are shifted right logical by the number of bits the elements in vector wt specify modulo the size of the element in bits. The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

SRLR.B
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = srlr(WR[ws]8i+7..8i, WR[wt]8i+2..8i, 8)
   endfor
SRLR.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = srlr(WR[ws]16i+15..16i, WR[wt]16i+3..16i, 16)
   endfor
SRLR.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = srlr(WR[ws]32i+31..32i, WR[wt]32i+4..32i, 32)
   endfor
SRLR.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = srlr(WR[ws]64i+63..64i, WR[wt]64i+5..64i, 64)
   endfor
function srlr(ts, n, b)
   if n = 0 then
      return ts
   else
      return (0n || tsb-1..n) + tsn-1
   endif
endfunction srlr

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.