Encoding:

Format:

FSOR.df 

FSOR.W wd,ws,wt

FSOR.D wd,ws,wt

Purpose:

Vector Floating-Point Signaling Compare Ordered

Vector to vector floating-point signaling compare ordered; if true all destination bits are set, otherwise clear.

Description:

wd[i] = ws[i] !?(signaling) wt[i]

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are ordered, i.e. both elements are not NaN values, otherwise set all bits to 0.

The signaling compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FSOR.W
   for i in 0 .. WRLEN/32-1
      c = OrderedSigFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FSOR.D
   for i in 0 .. WRLEN/64-1
      c = OrderedSigFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function OrderedSigFP(tt, ts, n)
   /* Implementation defined signaling ordered compare operation. */
endfunction OrderedSigFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.