COP0 010000 |
V 00011 |
rt |
rd |
010 |
00000 |
sel |
6 |
5 |
5 |
5 |
3 |
5 |
3 |
MTGC0 rt, rd, sel |
MIPS32 |
Move to Guest Coprocessor 0 |
Move to Guest Coprocessor 0
To move the contents of a general register to a guest coprocessor 0 register.
Guest.CPR[0, rd, sel] = GPR[rt]
The contents of general register rt are loaded into the guest context coprocessor 0 register speciied by the combination of rd and sel. Not all guest context coprocessor 0 registers support the sel ield. In those instances, the sel ield must be set to zero.
When the guest context coprocessor 0 destination register speciied is the EntryLo0 or the EntryLo1 register, bits
31:30 appear as the RI/XI ields of the destination register. This feature supports 32-bit addressing mode compatibility on a MIPS64 system.
The results are UNDEFINED if guest context coprocessor 0 does not contain the register as speciied by rd and sel or the destination register is the Guest.Count register, which is read-only
The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.
MTGC0 must behave exactly the same as the corresponding guest MTC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the write must complete, if the register is Reserved for Architecture/Implementation or is Not Available, the write is ignored, if the register is Shared (such as WatchHi) then the write always completes but does not effect ields invisible to guest.
In a 64-bit processor, the MTGC0 instruction writes all 64 bits of register rt into the guest context coprocessor register speciied by rd and sel if that register is a 64-bit register.
If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.
if IsCoprocessorEnabled(0) then if (Config3VZ = 0) then SignalException(ReservedInstruction, 0) break endif data = GPR[rt] reg = rd if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then Guest.CPR[0,reg,sel]29..0 = data29..0 Guest.CPR[0,reg,sel]63 = data31 Guest.CPR[0,reg,sel]62 = data30 Guest.CPR[0,reg,sel]61:30 = 032 else if (Width(CPR[0,reg,sel]) = 64) then Guest.CPR[0,reg,sel] = data else endif else SignalException(CoprocessorUnusable, 0) endif
Coprocessor Unusable
Reserved Instruction