Encoding:

MSA

011110

001

df

wt

ws

wd

3R

001101

6

3

2

5

5

5

6

Format: 

SRA.df

Vector Shift Right Arithmetic

SRA.B wd,ws,wt

MSA

Vector Shift Right Arithmetic

SRA.H wd,ws,wt

MSA

Vector Shift Right Arithmetic

SRA.W wd,ws,wt

MSA

Vector Shift Right Arithmetic

SRA.D wd,ws,wt

MSA

Vector Shift Right Arithmetic

Purpose:

Vector Shift Right Arithmetic

Vector bit count shift right arithmetic.

Description: 

wd[i] = ws[i] >> wt[i]

The elements in vector ws are shifted right arithmetic by the number of bits the elements in vector wt specify modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

SRA.B
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = (WR[ws]8i+7)t || WR[ws]8i+7..8i+t
   endfor
SRA.H
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = (WR[ws]16i+15)t || WR[ws]16i+15..16i+t
   endfor
SRA.W
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = (WR[ws]32i+31)t || WR[ws]32i+31..32i+t
   endfor
SRA.D
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = (WR[ws]64i+63)t || WR[ws]64i+63..64i+t
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.