Encoding:

Format:

PREFX hint, index(base)

Purpose:

Prefetch Indexed

To move data between memory and cache.

Description:

 prefetch_memory[GPR[base] + GPR[index]]

PREFX adds the contents of GPR index to the contents of GPR base to form an effective byte address. The hint field supplies information about the way the data is expected to be used.

The only functional difference between the PREF and PREFX instructions is the addressing mode implemented by the two. Refer to the PREF instruction for all other details, including the encoding of the hint field.

Restrictions:

Availability and Compatibility:

Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required by

MIPS32 Release 2 and subsequent versions of MIPS32. When required, required whenever FPU is present, whether a

32-bit or 64-bit FPU, whether in 32-bit or 64-bit FP Register Mode (FIR_F64=0 or 1, Status_FR=0 or 1).

This instruction has been removed in Release 6.

Operation:

vAddr = GPR[base] + GPR[index]
(pAddr, CCA) = AddressTranslation(vAddr, DATA, LOAD)
Prefetch(CCA, pAddr, vAddr, DATA, hint)

Exceptions:

Coprocessor Unusable, Reserved Instruction, Bus Error, Cache Error

Programming Notes:

The PREFX instruction is only available on processors that implement floating point and should never by generated by compilers in situations other than those in which the corresponding load and store indexed floating point instructions are generated.

Refer to the corresponding section in the PREF instruction description.