Encoding:

Format:

FSUEQ.df 

FSUEQ.W wd,ws,wt

FSUEQ.D wd,ws,wt

Purpose:

Vector Floating-Point Signaling Compare Unordered or Equal

Vector to vector floating-point signaling compare for unordered or equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] =?(signaling) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are unordered or equal, otherwise set all bits to 0.

The signaling compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM

2008.

Operation:

FSUEQ.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedSigFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = EqualSigFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d)32
   endfor
FSUEQ.D
   for i in 0 .. WRLEN/64-1
      c = UnorderedSigFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = EqualSigFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = (c | d)64
   endfor
function UnorderedSigFP(tt, ts, n)
   /* Implementation defined signaling unordered compare operation. */
endfunction UnorderedSigFP
function EqualSigFP(tt, ts, n)
   /* Implementation defined signaling equal compare operation. */
endfunction EqualSigFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.