Encoding:

Format:

TLBWI

Purpose:

Write Indexed TLB Entry

To write a TLB entry indexed by the Index register.

Description:

The TLBWI instruction is unmodiied from the base architecture, except in an implementation supporting GuestID:

When executing in Guest mode, GuestCtl1_ID is written in the guest TLB entry.

• When executing in Root mode GuestCtl1_RID is written in the root TLB entry.

• It is expected that a Guest entry in the Root TLB must have its Global(G) bit set to 1 on a TLB write. This is because the ASID ield is not applicable for a Guest entry in the Root TLB.

If EHINV is implemented, the TLBWI instruction also acts as an explicit TLB entry invalidate operation. The TLB entry pointed to by the Index register is marked invalid when EntryHIEHINV=1.

When EntryHI_EHINV=1, no machine check generating error conditions exist.

Restrictions:

Unmodiied from the base architecture.

Operation:

if IsCoprocessorEnabled(0) then
   i = Index
   if ( Config4IE >= 2) then
      TLB[i]hardware_invalid = 0
      if (EntryHIEHINV=1) then
         TLB[i]hardware_invalid = 1
      endif
   endif
   TLB[i]Mask = PageMaskMask
   TLB[i]R = EntryHiR
   TLB[i]VPN2 = EntryHiVPN2 and not PageMaskMask # Implementation dependent
   TLB[i]ASID = EntryHiASID
   if (GuestCtl0G1) then
         if ((GuestCtl0RAD=0) and IsRootMode() and (GuestCtl1RID != 0))
             TLB[i]G = 1
         else
             TLB[i]G = EntryLo1G and EntryLo0G
         endif
   else
         TLB[i]G = EntryLo1G and EntryLo0G
   endif
   if ( IsRootMode() ) then
      TLB[i]GuestID = GuestCtl1RID
      TLB[i]GuestID = GuestCtl1ID
   endif
   TLB[i]PFN1 = EntryLo1PFN and not PageMaskMask # Implementation dependent
   TLB[i]C1 = EntryLo1C
   TLB[i]D1 = EntryLo1D
   TLB[i]V1 = EntryLo1V
   TLB[i]PFN0 = EntryLo0PFN and not PageMaskMask # Implementation dependent
   TLB[i]C0 = EntryLo0C
   TLB[i]D0 = EntryLo0D
   TLB[i]V0 = EntryLo0V
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Unmodiied from the base architecture.