Encoding:

Format:

CLT_U.df 

CLT_U.B wd,ws,wt

CLT_U.H wd,ws,wt

CLT_U.W wd,ws,wt

CLT_U.D wd,ws,wt

Purpose:

Vector Compare Unsigned Less Than

Vector to vector compare for unsigned less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < wt[i])

Set all bits to 1 in wd elements if the corresponding ws elements are unsigned less than wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLT_U.B
   for i in 0 .. WRLEN/8-1
      c = (0 || WR[ws]8i+7..8i) < (0 || WR[wt]8i+7..8i)
      WR[wd]8i+7..8i = c8
   endfor
CLT_U.H
   for i in 0 .. WRLEN/16-1
      c = (0 || WR[ws]16i+15..16i) < (0 || WR[wt]16i+15..16i)
      WR[wd]16i+15..16i = c16
   endfor
CLT_U.W
   for i in 0 .. WRLEN/32-1
      c = (0 || WR[ws]__32i+31..32i_)_ < (0 || WR[wt]32i+31..32i)
      WR[wd]32i+31..32i = c32
   endfor
CLT_U.D
   for i in 0 .. WRLEN/64-1
      c = (0 || WR[ws]64i+63..64i) < (0 || WR[wt]64i+63..64i)
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.