Encoding:

MSA

011110

011

df

wt

ws

wd

3R

001101

6

3

2

5

5

5

6

Format: 

BCLR.df

Vector Bit Clear

BCLR.B wd,ws,wt

MSA

Vector Bit Clear

BCLR.H wd,ws,wt

MSA

Vector Bit Clear

BCLR.W wd,ws,wt

MSA

Vector Bit Clear

BCLR.D wd,ws,wt

MSA

Vector Bit Clear

Purpose:

Vector Bit Clear

Vector selected bit position clear in each element.

Description: 

wd[i] = bit_clear(ws[i], wt[i])

Clear (set to 0) one bit in each element of vector ws. The bit position is given by the elements in wt modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

BCLR.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+7..8i and (17-t || 0 || 1t)
   endfor
BCLR.:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+15..16i and (115-t || 0 || 1t)
   endfor
BCLR.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+31..32i and (131-t || 0 || 1t)
   endfor
BCLR.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+63..64i and (163-t || 0 || 1t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.