SPECIAL3 011111 |
0 00000 |
rt |
rd |
SEB 10000 |
BSHFL 100000 |
6 |
5 |
5 |
5 |
5 |
6 |
SEB rd, rt |
MIPS32 Release 2 |
Sign-Extend Byte |
Sign-Extend Byte
To sign-extend the least significant byte of GPR rt and store the value into GPR rd.
GPR[rd] = SignExtend(GPR[rt]7..0)
The least significant byte from GPR rt is sign-extended and stored in GPR rd.
Prior to architecture Release 2, this instruction resulted in a Reserved Instruction exception.
If GPR rt does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is
UNPREDICTABLE.
if NotWordValue(GPR[rt]) then UNPREDICTABLE endif GPR[rd] = sign_extend(GPR[rt]7..0)
Reserved Instruction
For symmetry with the SEB and SEH instructions, you expect that there would be ZEB and ZEH instructions that zero-extend the source operand and expect that the SEW and ZEW instructions would exist to sign- or zero-extend a word to a doubleword. These instructions do not exist because there are functionally-equivalent instructions already in the instruction set. The following table shows the instructions providing the equivalent functions.
Expected InstructionFunctionEquivalent Instruction
Zero-Extend Byte
ZEB rx,ry ANDI rx,ry,0xFF
Zero-Extend Halfword
ZEH rx,ry ANDI rx,ry,0xFFFF
Sign-Extend Word
SEW rx,ry SLL rx,ry,0 ZEW rx,rx1Zero-Extend Word DINSP32 rx,r0,32,32
1. The equivalent instruction uses rx for both source and destination, so the expected instruction is limited to one register