SDR 101101 |
base |
rt |
offset |
6 |
5 |
5 |
16 |
SDR rt, offset(base) |
MIPS64, removed in Release 6 |
Store Doubleword Right |
Store Doubleword Right
To store the least-significant part of a doubleword to an unaligned memory address.
memory[GPR[base] + offset] = Some_Bytes_From GPR[rt]
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the least-significant of 8 consecutive bytes forming a doubleword (DW) in memory, starting at an arbitrary byte boundary.
A part of DW, the least-significant 1 to 8 bytes, is in the aligned doubleword containing EffAddr. The same number of least-significant (right) bytes of GPR rt are stored into these bytes of DW.
Figure 3-25 illustrates this operation for big-endian byte ordering. The 8 consecutive bytes in 2..9 form an unaligned doubleword starting at location 2. A part of DW (2 bytes) is located in the aligned doubleword containing the leastsignificant byte at 9.
Release 6 removes the load/store-left/right family of instructions, and requires the system to support misaligned memory accesses.
vAddr = sign_extend(offset) + GPR[base] (pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE) pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor ReverseEndian3) If BigEndianMem = 0 then pAddr = pAddrPSIZE-1..3 || 03 endif bytesel = vAddr1..0 xor BigEndianCPU3 datadoubleword = GPR[rt]63-8*bytesel || 08*bytesel StoreMemory (CCA, DOUBLEWORD-byte, datadoubleword, pAddr, vAddr, DATA)
TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error, Reserved Instruction, Watch