Encoding:

Format:

SHRL.QB rd, rt, sa

Purpose:

Shift Right Logical Vector Quad Bytes

Element-wise logical right shift of four independent bytes in a vector data type by a fixed number of bits.

Description:

rd = sign_extend(rt31..24 >> sa) || (rt23..16 >> sa) || (rt15..8 >> sa) || (rt7..0 >> sa))

The four right-most byte values in register rt are each independently shifted right by sa bits and the sa most-significant bits of each value are set to zero. The four independent results are then written to the corresponding byte elements of destination register rd.

The sign of the left-most result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempD7..0 = shift8Right( GPR[rt]31..24, sa )
tempC7..0 = shift8Right( GPR[rt]23..16, sa )
tempB7..0 = shift8Right( GPR[rt]15..8, sa )
tempA7..0 = shift8Right( GPR[rt]7..0, sa )
GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function shift8Right( a7..0, s2..0 )
   if ( s2..0 = 0 ) then
      temp7..0 = a7..0
   else
      temp7..0 = ( 0s || a7..s )
   endif
   return temp7..0
endfunction shift8Right

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

To do a logical left shift of a word in a register without saturation, use the MIPS64 SLL instruction.