Encoding:

Format:

SRLI.df 

SRLI.B wd,ws,m

SRLI.H wd,ws,m

SRLI.W wd,ws,m

SRLI.D wd,ws,m

Purpose:

Immediate Shift Right Logical

Immediate bit count shift right logical.

Description:

wd[i] = ws[i] >> m

The elements in vector ws are shifted right logical by m bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

SRLI.B
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = 0t || WR[ws]8i+7..8i+t
   endfor
SRLI.H
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = 0t || WR[ws]16i+15..16i+t
   endfor
SRLI.W
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = 0t || WR[ws]32i+31..32i+t
   endfor
SRLI.D
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = 0t || WR[ws]64i+63..64i+t
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.