Encoding:

Format:

BC1ANY2F cc,offset

Purpose:

Branch on Any of Two Floating Point Condition Codes False

To test two consecutive floating point condition codes and do a PC-relative conditional branch

Description:

If FPConditionCode(CCn+1) = 0 or FPConditionCode(CCn) = 0, then branch

An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If either one of the two FP condition code bits CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed.

The CC specified must align to 2, so bit 18 must always be zero. For example, specifying a value of 4 will check if in UNPREeither one of CC5 or CC4 is 0 and branch accordingly. Specifying an illegally aligned CC will result

DICTABLE behavior.

An FP condition code is set by an FP compare instruction, C.cond.fmt and the MIPS-3D compare absolute instruction

CABS.cond.fmt.

Restrictions:

Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.

Operation:

This operation specification is for the general Branch On Any Two Condition operation with the tf (true/false) as a variables. The individual instructions BC1ANY2F and BC1ANY2T have a specific values for tf.

I:    condition = (FPConditionCode(cc) = 0) or
                   (FPConditionCode(cc+1) = 0)
      target_offset = (offset15)GPRLEN-(16+2)|| offset || 02
I+1:  if condition then
         PC = PC + target_offset
      endif

Exceptions:

Coprocessor Unusable, Reserved Instruction

Floating Point Exceptions:

Unimplemented Operation

Programming Notes:

With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register

(JR) instructions to branch to addresses outside this range.