COP1 010001 |
fmt 10110 |
0 00000 |
fs |
fd |
CVT.PW.PS 100100 |
6 |
5 |
5 |
5 |
5 |
6 |
CVT.PW.PS fd,fs |
MIPS-3D |
Floating Point Convert Paired Single to Paired Word |
Floating Point Convert Paired Single to Paired Word
To convert a FP paired-single value to a pair of 32-bit fixed point words
FPR[fd].PU = convert_and_round(FPR[fs].PU); FPR[fd].PL =convert_and_round(FPR[fs].PL)
The values in FPR fs,in format PS, are converted to a pair of values in 32-bit word fixed point format and rounded according to the current rounding mode in FCSR. The result is placed in FPR fd. The conversions of the two halves are done independently.
When either source value is Infinity, NaN, or rounds to an integer outside the range -231 to 231-1,the result cannot be represented correctly, an IEEE Invalid Operation condition exists, and the Invalid Operation flag is set in the
FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation exception is taken immediately. Otherwise,
the defaultresult, 231–1,is written to the correspond half of FPR fd which caused the exception.
The fields fs and fd must specify valid FPRs-fs for type PS and fd for type PW. If they are not valid,the resultis
UNPREDICTABLE. The format of the data in the specified operand register fs must be a value in format PS; if it is
not, the result is UNPREDICTABLE and the value in the operand FPR becomes UNPREDICTABLE.
The result of this instruction is UNPREDICTABLE if the processor is executing in 16 FP registers mode.
StoreFPR(fd, PW, ConvertFmt(ValueFPR(fs, PS)63..32, S, W) || ConvertFmt(ValueFPR(fs, PS)31..0, S, W) )
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions
Unimplemented Operation, Invalid Operation, Overflow, Inexact