COP1 010001 |
fmt |
ft |
fs |
cc |
0 |
A 0 |
FC 11 |
cond |
6 |
5 |
5 |
5 |
3 |
1 |
1 |
2 |
4 |
C.cond.fmt |
Floating Point Compare | |
C.cond.S cc, fs, ft |
MIPS32, removed in Release 6 |
Floating Point Compare |
C.cond.D cc, fs, ft |
MIPS32, removed in Release 6 |
Floating Point Compare |
C.cond.PS cc, fs, ft |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Compare |
Floating Point Compare
To compare FP values and record the Boolean result in a condition code.
FPConditionCode(cc) = FPR[fs] compare_cond FPR[ft]
The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The comparison is exact and neither overflows nor underflows.
If the comparison specified by the cond field of the instruction is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into condition code CC; true is 1 and false is 0.
In the cond field of the instruction: cond2..1 specify the nature of the comparison (equals, less than, and so on). cond0 specifies whether the comparison is ordered or unordered, that is, false or true if any operand is a NaN; cond3 indicates whether the instruction should signal an exception on QNaN inputs, or not (see Table 3.2).
C.cond.PS compares the upper and lower halves of FPR fs and FPR ft independently and writes the results into condition codes CC +1 and CC respectively. The CC number must be even. If the number is not even the operation of the instruction is UNPREDICTABLE.
If one of the values is an SNaN, or cond3 is set and at least one of the values is a QNaN, an Invalid Operation condition is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise, the Boolean result is written into condition code CC.
There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0.
The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal,
equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Boolean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP values in the equation. If the equal relation is true, for example, then all four example predicates above yield a true
result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result.
The fields fs and ft must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPREDICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
The result of C.cond.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU,.
The result of C.cond.PS is UNPREDICTABLE if the condition code number is odd.
This instruction has been removed in Release 6 and has been replaced by the ‘CMP.cond fmt’ instruction. Refer to the
CMP.cond fmt instruction in this manual for more information. Release 6 does not support Paired Single (PS).
if SNaN(ValueFPR(fs, fmt)) or SNaN(ValueFPR(ft, fmt)) or QNaN(ValueFPR(fs, fmt)) or QNaN(ValueFPR(ft, fmt)) then less = false equal = false unordered = true if (SNaN(ValueFPR(fs,fmt)) or SNaN(ValueFPR(ft,fmt))) or (cond3 and (QNaN(ValueFPR(fs,fmt)) or QNaN(ValueFPR(ft,fmt)))) then SignalException(InvalidOperation) endif else less = ValueFPR(fs, fmt) <fmt ValueFPR(ft, fmt) equal = ValueFPR(fs, fmt) =fmt ValueFPR(ft, fmt) unordered = false endif condition = (cond2 and less) or (cond1 and equal) or (cond0 and unordered) SetFPConditionCode(cc, condition)
For C.cond.PS, the pseudo code above is repeated for both halves of the operand registers, treating each half as an independent single-precision values. Exceptions on the two halves are logically ORed and reported together. The results of the lower half comparison are written to condition code CC; the results of the upper half comparison are written to condition code CC+1.
Coprocessor Unusable, Reserved Instruction
Unimplemented Operation, Invalid Operation
FP computational instructions, including compare, that receive an operand value of Signaling NaN raise the Invalid
Operation condition. Comparisons that raise the Invalid Operation condition for Quiet NaNs in addition to SNaNs permit a simpler programming model if NaNs are errors. Using these compares, programs do not need explicit code to check for QNaNs causing the unordered relation. Instead, they take an exception and allow the exception handling system to deal with the error when it occurs. For example, consider a comparison in which we want to know if two numbers are equal, but for which unordered would be an error.
# comparisons using explicit tests for QNaN c.eq.d $f2,$f4 # check for equal nop bc1t L2 # it is equal c.un.d $f2,$f4 # it is not equal, # but might be unordered bc1t ERROR # unordered goes off to an error handler # not-equal-case code here ... # equal-case code here L2: # -------------------------------------------------------------# comparison using comparisons that signal QNaN c.seq.d $f2,$f4 # check for equal nop bc1t L2 # it is equal nop # it is not unordered here ... # not-equal-case code here ... # equal-case code here