Encoding:

Format:

FSAF.df 

FSAF.W wd,ws,wt

FSAF.D wd,ws,wt

Purpose:

Vector Floating-Point Signaling Compare Always False

Vector to vector floating-point signaling compare always false; all destination bits are clear.

Description:

wd[i] = signalingFalse(ws[i], wt[i])

Set all bits to 0 in wd elements. Signaling and quiet NaN elements in ws or wt signal Invalid Operation exception.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FSAF.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = SignalingFALSE(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
FSAF.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = SignalingFALSE(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function SignalingFALSE(tt, ts, n)
   /* Implementation defined signaling and quiet NaN test */
   return 0
endfunction SignalingFALSE

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.