Encoding:

Format:

TLBP 

Purpose:

Probe TLB for Matching Entry

To find a matching entry in the TLB.

Description:

The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the Index register is set.

• In Release 1 of the Architecture, it is implementation dependent whether multiple TLB matches are detected on a

TLBP. However, implementations are strongly encouraged to report multiple TLB matches only on a TLB write.

• In Release 2 of the Architecture, multiple TLB matches may only be reported on a TLB write.

• In Release 3 of the Architecture, multiple TLB matches may be reported on either TLB write or TLB probe.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Release 6: Processors that include a Block Address Translation (BAT) or Fixed Mapping (FM) MMU (Config_MT = 2 or 3), the operation of this instruction causes a Reserved Instruction exception (RI).

Operation:

Index = 1 || UNPREDICTABLE31
for i in 00 ... TLBEntries-1
   if ((TLB[i]VPN2 and not (TLB[i]Mask)) =
               (EntryHiVPN2 and not (TLB[i]Mask))) and
       (TLB[i]R = EntryHiR) and
       ((TLB[i]G = 1) or (TLB[i]ASID = EntryHiASID)) then
       Index = i
   endif
endfor

Exceptions:

Coprocessor Unusable, Machine Check