COP2 010010 |
BC 01000 |
cc |
nd 0 |
tf 0 |
offset |
6 |
5 |
3 |
1 |
1 |
16 |
BC2F cc, offset |
MIPS32, removed in Release 6 |
Branch on COP2 False |
Branch on COP2 False
To test a COP2 condition code and do a PC-relative conditional branch.
if COP2Condition(cc) = 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by cc is false (0), the program branches to the effective target address after the instruction in the delay slot is executed.
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
This instruction has been removed in Release 6.
I: condition = COP2Condition(cc) = 0 target_offset = (offset15)GPRLEN-(16+2) || offset || 02 I+1: if condition then PC = PC + target_offset endif
Coprocessor Unusable, Reserved Instruction
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register
(JR) to branch to addresses outside this range.
This instruction has been replaced by the BC2EQZ instruction. Refer to the 'BC2EQZ' instruction in this manual for more information.