Encoding:

MIPS64 pre-Release 6

MIPS64 Release 6

Format:

LLD rt, offset(base)

Purpose:

Load Linked Doubleword

To load a doubleword from memory for an atomic read-modify-write

Description:

 GPR[rt] = memory[GPR[base] + offset]

The LLD and SCD instructions provide primitives to implement atomic read-modify-write (RMW) operations for synchronizable memory locations.

The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed into GPR rt. The signed offset is added to the contents of GPR base to form an effective address.

This begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor.

When an LLD is executed it starts the active RMW sequence and replaces any other sequence that was active. The

RMW sequence is completed by a subsequent SCD instruction that either completes the RMW sequence atomically and succeeds, or does not complete and fails.

Executing LLD on one processor does not cause an action that, by itself, would cause an SCD for the same block to fail on another processor.

An execution of LLD does not have to be followed by execution of SCD; a program is free to abandon the RMW sequence without attempting a write.

Restrictions:

The addressed location must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result in UNPREDICTABLE. Which storage is synchronizable is a function of both CPU and system implementations. See the documentation of the SCD instruction for the formal definition.

The effective address must be naturally-aligned. If any of the 3 least-significant bits of the effective address is nonzero, an Address Error exception occurs.

Providing misaligned support for Release 6 is not a requirement for this instruction.

Availability and Compatibility:

This instruction has been reallocated an opcode in Release 6.

Operation:

vAddr = sign_extend(offset) + GPR[base]
if vAddr2..0 != 03 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memdoubleword = LoadMemory (CCA, DOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt] = memdoubleword
LLbit = 1

Exceptions:

TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Watch