Encoding:

Format:

JIC rt, offset 

Purpose:

Jump Indexed, Compact

Description:

PC =( GPR[rt] + sign_extend( offset ) )

The branch target is formed by sign extending the offset field of the instruction and adding it to the contents of GPR rt.

The offset is NOT shifted, that is, each bit of the offset is added to the corresponding bit of the GPR.

For processors that do not implement the MIPS16e or microMIPS ISA:

• Jump to the effective target address derived from GPR rt and the offset. If the target address is not 4-byte aligned, an Address Error exception will occur when the target address is fetched.

For processors that do implement the MIPS16e or microMIPS ISA:

• Jump to the effective target address derived from GPR rt and the offset. Set the ISA Mode bit to bit 0 of the effective address. Set bit 0 of the target address to zero. If the target ISA Mode bit is 0 and the target address is not 4byte aligned, an Address Error exception will occur when the target instruction is fetched.

Compact jumps do not have a delay slot. The instruction after the jump is NOT executed when the jump is executed.

Restrictions:

This instruction is an unconditional, always taken, compact jump, and hence has neither a delay slot nor a forbidden slot. The instruction after the jump is not executed when the jump is executed.

Availability and Compatibility:

This instruction is introduced by and required as of Release 6.

Release 6 instructions JIC and BEQZC differ only in the rs field. JIC and BEQZC occupy the same encoding as preRelease 6 instruction LDC2, which is recoded in Release 6.

Exceptions:

None

Operation:

temp = GPR[rt] + sign_extend(offset)
if (Config3ISA = 0) and (Config1CA = 0) then 
      PC = temp 
   else
      PC = (tempGPRLEN-1..1 || 0)
      ISAMode = temp0
   endif

Programming Notes:

JIC does NOT shift the offset before adding it the register. This can be used to eliminate tags in the least significant bits that would otherwise produce misalignment. It also allows JIALC to be used as a substitute for the JALX instruction, removed in Release 6, where the lower bits of the target PC, formed by the addition of GPR[rt] and the unshifted offset, specify the target ISAmode.