Encoding:

MSA

011110

00000

wt

ws

wd

VEC

011110

6

5

5

5

5

6

Format: 

AND.V

Vector Logical And

AND.V wd,ws,wt

MSA

Vector Logical And

Purpose:

Vector Logical And

Vector by vector logical and.

Description: 

wd = ws AND wt

Each bit of vector ws is combined with the corresponding bit of vector wt in a bitwise logical AND operation. The result is written to vector wd.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

 WR[wd] = WR[ws] and WR[wt]

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.