MSA 011110 |
1011 |
df |
wt |
ws |
wd |
3RF 011100 |
6 |
4 |
1 |
5 |
5 |
5 |
6 |
FSNE.df |
Vector Floating-Point Signaling Compare Not Equal | |
FSNE.W wd,ws,wt |
MSA |
Vector Floating-Point Signaling Compare Not Equal |
FSNE.D wd,ws,wt |
MSA |
Vector Floating-Point Signaling Compare Not Equal |
Vector Floating-Point Signaling Compare Not Equal
Vector to vector floating-point signaling compare for not equal; if true all destination bits are set, otherwise clear.
wd[i] = (ws[i] !=(signaling) wt[i])
Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are not equal, otherwise set all bits to 0.
The signaling compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754TM-2008.
The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in
MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to
0.
The operands are values in floating-point data format df. The results are values in integer data format df.
Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754TM2008.
FSNE.W for i in 0 .. WRLEN/32-1 c = NotEqualSigFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32) WR[wd]32i+31..32i = c32 endfor FSNE.D for i in 0 .. WRLEN/64-1 c = NotEqualSigFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64) WR[wd]64i+63..64i = c64 endfor function NotEqualSigFP(tt, ts, n) /* Implementation defined signaling not equal compare operation. */ endfunction NotEqualSigFP
Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.