Encoding:

Format:

LDXC1 fd, index(base)

Purpose:

Load Doubleword Indexed to Floating Point

To load a doubleword from memory to an FPR (GPR+GPR addressing)

Description:

 FPR[fd] = memory[GPR[base] + GPR[index]]

The contents of the 64-bit doubleword at the memory location specified by the aligned effective address are fetched and placed in FPR fd. The contents of GPR index and GPR base are added to form the effective address.

Restrictions:

An Address Error exception occurs if EffectiveAddress_2..0 != 0 (not doubleword-aligned). Availability and Compatibility:

This instruction has been removed in Release 6.

Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required in

MIPS32 Release 2 and all subsequent versions of MIPS32. When required, required whenever FPU is present, whether a 32-bit or 64-bit FPU, whether in 32-bit or 64-bit FP Register Mode (FIRF64=0 or 1, StatusFR=0 or 1).

Operation:

vAddr = GPR[base] + GPR[index]
if vAddr2..0 != 03 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memdoubleword = LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA)
paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02)
memlsw = LoadMemory(CCA, WORD, pAddr, vAddr, DATA)
paddr = paddr xor 0b100
memmsw = LoadMemory(CCA, WORD, pAddr, vAddr+4, DATA)
memdoubleword = memmsw || memlsw
StoreFPR(fd, UNINTERPRETED_DOUBLEWORD, memdoubleword)

Exceptions:

TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Coprocessor Unusable, Watch