Encoding:

Format:

SWRE rt, offset(base)

Purpose:

Store Word Right EVA

To store the least-significant part of a word to an unaligned user mode virtual address while operating in kernel mode.

Description:

 memory[GPR[base] + offset] = GPR[rt]

The 9-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the least-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.

A part of W (the least-significant 1 to 4 bytes) is in the aligned word containing EffAddr. The same number of the least-significant (right) bytes from the word in GPR rt are stored into these bytes of W.

If GPR rt is a 64-bit register, the source word is the low word of the register.

The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W (2 bytes) is contained in the aligned word containing the least-significant byte at 5.

Restrictions:

Only usable when access to Coprocessor0 is enabled and when accessing an address within a segment configured using UUSK, MUSK or MUSUK access mode.

Availability and Compatibility:

Release 6 removes the load/store-left/right family of instructions, and requires the system to support misaligned memory accesses.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor ReverseEndian3)
If BigEndianMem = 0 then
   pAddr = pAddrPSIZE-1..2 || 02
endif
byte = vAddr1..0 xor BigEndianCPU2
if (vAddr2 xor BigEndianCPU) = 0 then
   datadoubleword = 032 || GPR[rt]31-8*byte..0 || 08*byte
else
   datadoubleword = GPR[rt]31-8*byte..0 || 08*byte || 032
endif
dataword = GPR[rt]31-8*byte || 08*byte
StoreMemory(CCA, WORD-byte, datadoubleword, pAddr, vAddr, DATA)

Exceptions:

TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error, Watch, Coprocessor Unusable