Encoding:

SPECIAL

000000

rs

rt

rd

000

sa

LSA

000101

SPECIAL

000000

rs

rt

rd

000

sa

DLSA

010101

6

5

5

5

3

2

6

Format: 

LSA DLSA

Load Scaled Address, Doubleword Load Scaled Address

LSA rd,rs,rt,sa

MIPS32 Release 6

Load Scaled Address, Doubleword Load Scaled Address

DLSA rd,rs,rt,sa

MIPS64 Release 6

Load Scaled Address, Doubleword Load Scaled Address

Purpose:

Load Scaled Address, Doubleword Load Scaled Address

Description: 

LSA:  GPR[rd] = sign_extend.32( (GPR[rs] << (sa+1)) + GPR[rt] )
DLSA: GPR[rd] = (GPR[rs] << (sa+1)) + GPR[rt]

LSA adds two values derived from registers rs and rt, with a scaling shift on rs. The scaling shift is formed by adding 1 to the 2-bit sa field, which is interpreted as unsigned. The scaling left shift varies from 1 to 5, corresponding to multiplicative scaling values of <=2, <=4, <=8, <=16, bytes, or 16, 32, 64, or 128 bits.

LSA is a MIPS32 compatible instruction, sign extending its result from bit 31 to bit 63.

DLSA is a MIPS64 compatible instruction, performing the scaled index calculation fully 64-bits wide.

Restrictions:

LSA: None

DLSA: Reserved Instruction exception if 64-bit instructions are not enabled.

Availability and Compatibility:

LSA instruction is introduced by and required as of Release 6.

DLSA instruction is introduced by and required as of Release 6.

Operation 

LSA:  GPR[rd] = sign_extend.32( GPR[rs] << (sa+1) + GPR[rt] )
DLSA: GPR[rd] = GPR[rs] << (sa+1) + GPR[rt]

Exceptions:

LSA: None

DLSA: Reserved Instruction