Encoding:

Format:

PRECEU.PH.QBLA rd, rt

Purpose:

Precision Expand Two Unsigned Bytes to Unsigned Halfword Values

Expand the precision of two unsigned integer byte values taken from the two left-alternate aligned positions of a quad byte vector to create four unsigned halfword values.

Description:

rd = sign_extend(expand_prec8u16(rt31..24) || expand_prec8u16(rt15..8))

The two left-alternate aligned unsigned integer byte values from the four right-most byte elements in register rt are each expanded to unsigned halfword values and written to destination register rd. The precision expansion is achieved by pre-pending eight most-significant zero bits to the original byte value to generate each 16 bit unsigned halfword value.

The sign of the left-most result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = 08 || GPR[rt]31..24
tempA15..0 = 08 || GPR[rt]15..8
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled