MSA 011110 |
001 |
df/m |
ws |
wd |
BIT 001001 |
6 |
3 |
7 |
5 |
5 |
6 |
SRAI.df |
Immediate Shift Right Arithmetic | |
SRAI.B wd,ws,m |
MSA |
Immediate Shift Right Arithmetic |
SRAI.H wd,ws,m |
MSA |
Immediate Shift Right Arithmetic |
SRAI.W wd,ws,m |
MSA |
Immediate Shift Right Arithmetic |
SRAI.D wd,ws,m |
MSA |
Immediate Shift Right Arithmetic |
Immediate Shift Right Arithmetic
Immediate bit count shift right arithmetic.
wd[i] = ws[i] >> m
The elements in vector ws are shifted right arithmetic by m bits. The result is written to vector wd.
The operands and results are values in integer data format df.
No data-dependent exceptions are possible.
SRAI.B t = m for i in 0 .. WRLEN/8-1 WR[wd]8i+7..8i = (WR[ws]8i+7)t || WR[ws]8i+7..8i+t endfor SRAI.H t = m for i in 0 .. WRLEN/16-1 WR[wd]16i+15..16i = (WR[ws]16i+15)t || WR[ws]16i+15..16i+t endfor SRAI.W t = m for i in 0 .. WRLEN/32-1 WR[wd]32i+31..32i = (WR[ws]32i+31)t || WR[ws]32i+31..32i+t endfor SRAI.D t = m for i in 0 .. WRLEN/64-1 WR[wd]64i+63..64i = (WR[ws]64i+63)t || WR[ws]64i+63..64i+t endfor
Reserved Instruction Exception, MSA Disabled Exception.