MSA 011110 |
001 |
df |
wt |
ws |
wd |
3R 010101 |
6 |
3 |
2 |
5 |
5 |
5 |
6 |
SRAR.df |
Vector Shift Right Arithmetic Rounded | |
SRAR.B wd,ws,wt |
MSA |
Vector Shift Right Arithmetic Rounded |
SRAR.H wd,ws,wt |
MSA |
Vector Shift Right Arithmetic Rounded |
SRAR.W wd,ws,wt |
MSA |
Vector Shift Right Arithmetic Rounded |
SRAR.D wd,ws,wt |
MSA |
Vector Shift Right Arithmetic Rounded |
Vector Shift Right Arithmetic Rounded
Vector bit count shift right arithmetic with rounding
wd[i] = ws[i] >>(rounded) wt[i]
The elements in vector ws are shifted right arithmetic by the number of bits the elements in vector wt specify modulo the size of the element in bits. The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector wd.
The operands and results are values in integer data format df.
No data-dependent exceptions are possible.
SRAR.B for i in 0 .. WRLEN/8-1 WR[wd]8i+7..8i = srar(WR[ws]8i+7..8i, WR[wt]8i+2..8i, 8) endfor SRAR.H for i in 0 .. WRLEN/16-1 WR[wd]16i+15..16i = srar(WR[ws]16i+15..16i, WR[wt]16i+3..16i, 16) endfor SRAR.W for i in 0 .. WRLEN/32-1 WR[wd]32i+31..32i = srar(WR[ws]32i+31..32i, WR[wt]32i+4..32i, 32) endfor SRAR.D for i in 0 .. WRLEN/64-1 WR[wd]64i+63..64i = srar(WR[ws]64i+63..64i, WR[wt]64i+5..64i, 64) endfor function srar(ts, n, b) if n = 0 then return ts else return ((tsb-1)n || tsb-1..n) + tsn-1 endif endfunction srar
Reserved Instruction Exception, MSA Disabled Exception.