Encoding:

Format:

MTC0 rt, rd, sel

Purpose:

Move to Coprocessor 0

To move the contents of a general register to a coprocessor 0 register.

Description:

 CPR[0, rd, sel] = GPR[rt]

The contents of general register rt are loaded into the coprocessor 0 register specified by the combination of rd and

sel. Not all coprocessor 0 registers support the sel field. In those instances, the sel field must be set to zero.

When the CP0 destination register specified is the EntryLo0 or the EntryLo1 register, bits 31:30 appear in the RI/XI fields of the destination register. This feature supports MIPS32 backward compatibility on a MIPS64 implementation.

In Release 5, for a 32-bit processor, the MTC0 instruction writes all zeroes to the high-order bits of selected CP0 registers that have been extended beyond 32 bits. This is required for compatibility with legacy software that does not use MTHC0, yet has hardware support for extended CP0 registers (such as for Extended Physical Addressing (XPA)).

Because MTC0 overwrites the result of MTHC0, software must first read the high-order bits before writing the loworder bits, then write the high-order bits back either modified or unmodified. For initialization of an extended register, software may first write the low-order bits, then the high-order bits, without first reading the high-order bits.

Restrictions:

Pre-Release 6: The results are UNDEFINED if coprocessor 0 does not contain a register as specified by rd and sel.

Release 6: Writes to a register that is reserved or not defined for the current core configuration are ignored.

Operation:

data = GPR[rt]
reg = rd
if IsCoprocessorRegisterImplemented (0, reg, sel) then
   if (reg,sel = EntryLo1 or EntryLo0) then
      CPR[0,reg,sel]29..0 = data29..0
      CPR[0,reg,sel]63 = data31
      CPR[0,reg,sel]62 = data30
      CPR[0,reg,sel]61:30 = 032
   elseif (Width(CPR[0,reg,sel]) = 64) then
      CPR[0,reg,sel] = data
   else
      CPR[0,reg,sel] = data31..0
      if (Config5XPA = 1) then
         // The most-significant bit may vary by register. Only supported
         // bits should be written 0. Extended LLAddr is not written with 0s,
         // as it is a read-only register. BadVAddr is not written with 0s, as
         // it is read-only
         if (Config3LPA = 1) then
             if (reg,sel = EntryLo0 or EntryLo1) then CPR[0,reg,sel]63:32 = 032
             endif
             if (reg,sel = MAAR) then CPR[0,reg,sel]63:32 = 032 endif
                // TagLo is zeroed only if the implementation-dependent bits
                // are writeable
             if (reg,sel = TagLo) then CPR[0,reg,sel]63:32 = 032 endif
             if (Config3VZ = 1) then 
                if (reg,sel = EntryHi) then CPR[0,reg,sel]63:32 = 032 endif
             endif
          endif
      endif
   endif
else
   if ArchitectureRevision() >= 6 then
   // nop (no exceptions, coprocessor state not modified)
   else
      UNDEFINED
   endif
endif

Exceptions:

Coprocessor Unusable, Reserved Instruction