Encoding:

Format:

DIV MOD DIVU MODU DDIV DMOD DDIVU DMODU 

DIV rd,rs,rt

MOD rd,rs,rt

DIVU rd,rs,rt

MODU rd,rs,rt

DDIV rd,rs,rt

DMOD rd,rs,rt

DDIVU rd,rs,rt

DMODU rd,rs,rt

Purpose:

Divide Integers (with result to GPR)

DIV: Divide Words Signed

MOD: Modulo Words Signed

DIVU: Divide Words Unsigned

MODU: Modulo Words Unsigned

DDIV: Divide Doublewords Signed

DMOD: Modulo Doublewords Signed

DDIVU: Divide Doublewords Unsigned

DMODU: Modulo Doublewords Unsigned

Description:

DIV:  GPR[rd] = sign_extend.32( divide.signed( GPR[rs], GPR[rt] )
MOD:  GPR[rd] = sign_extend.32( modulo.signed( GPR[rs], GPR[rt] )
DIVU:  GPR[rd] = sign_extend.32( divide.unsigned( GPR[rs], GPR[rt] )
MODU:  GPR[rd] = sign_extend.32( modulo.unsigned( GPR[rs], GPR[rt] )
DDIV:  GPR[rd] = divide.signed( GPR[rs], GPR[rt] )
DMOD:  GPR[rd] = modulo.signed( GPR[rs], GPR[rt] )
DDIVU: GPR[rd] = divide.unsigned( GPR[rs], GPR[rt] )
DMODU: GPR[rd] = modulo.unsigned( GPR[rs], GPR[rt] )

The Release 6 divide and modulo instructions divide the operands in GPR rs and GPR rt, and place the quotient or remainder in GPR rd.

For each of the div/mod operator pairs DIV/M OD, DIVU/MODU, DDIV/DMOD, DDIVU/DMODU the results satisfy the equation (A div

B)*B + (A mod B) = A, where (A mod B) has same sign as the dividend A, and
abs(A mod B) < abs(B). This equation uniquely defines the results. 

NOTE: if the divisor B=0, this equation cannot be satisfied, and the result is UNPREDICTABLE. This is commonly called "truncated division".

DIV performs a signed 32-bit integer division, and places the 32-bit quotient result in the destination register.

MOD performs a signed 32-bit integer division, and places the 32-bit remainder result in the destination register. The remainder result has the same sign as the dividend.

DIVU performs an unsigned 32-bit integer division, and places the 32-bit quotient result in the destination register.

MODU performs an unsigned 32-bit integer division, and places the 32-bit remainder result in the destination register.

DDIV performs a signed 64-bit integer division, and places the 64-bit quotient result in the destination register.

DMOD performs a signed 64-bit integer division, and places the 64-bit remainder result in the destination register.

The remainder result has the same sign as the dividend.

DDIVU performs an unsigned 64-bit integer division, and places the 64-bit quotient result in the destination register.

DMODU performs an unsigned 64-bit integer division, and places the 64-bit remainder result in the destination register.

Restrictions:

If the divisor in GPR rt is zero, the result value is UNPREDICTABLE.

On a 64-bit CPU, the 32-bit signed divide (DIV) and modulo (MOD) instructions are UNPREDICTABLE if inputs are not signed extended 32-bit integers.

Special provision is made for the inputs to unsigned 32-bit divide and modulo on a 64-bit CPU. Since many 32-bit instructions sign extend 32 bits to 64 even for unsigned computation, properly sign extended numbers must be accepted as input, and truncated to 32 bits, clearing bits 32-63. However, it is also desirable to accept zero extended

32-bit integers, with bits 32-63 all 0.

On a 64-bit CPU, DIVU and MODU are UNPREDICTABLE if their inputs are not zero or sign extended 32-bit integers.

On a 64-bit CPU, the 32-bit divide and modulo instructions, both signed and unsigned, sign extend the result as if it is a 32-bit signed integer.

DDIV, DMOD, DDIVU, DMODU: Reserved Instruction exception if 64-bit instructions are not enabled.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

Release 6 divide instructions have the same opcode mnemonic as the pre-Release 6 divide instructions (DIV, DIVU,

DDIV, DDIVU). The instruction encodings are different, as are the instruction semantics: the Release 6 instruction produces only the quotient, whereas the pre-Release 6 instruction produces quotient and remainder in HI/LO registers respectively, and separate modulo instructions are required to obtain the remainder.

The assembly syntax distinguishes the Release 6 from the pre-Release 6 divide instructions. For example, Release 6

"DIVrd,rs,rt" specifies 3 register operands, versus pre-Release 6 "DIV rs,rt", which has only two register arguments, with the HI/LO registers implied.

Some assemblers accept the pseudo-instruction syntax

"DIVrd,rs,rt" and expand it to do "DIV rs,rt;MFHI rd". Phrases such as "DIV with GPR output" and

"DIV with HI/LO output" may be used when disambiguation is necessary.

Pre-Release 6 divide instructions that produce quotient and remainder in the HI/LO registers produce a Reserved

Instruction exception on Release 6. In the future, the instruction encoding may be reused for other instructions.

Programming Notes:

Because the divide and modulo instructions are defined to not trap if dividing by zero, it is safe to emit code that checks for zero-divide after the divide or modulo instruction.

Operation

DDIV, DMOD, DDIVU, DMODU:
 if not Are64bitOperationsEnabled then SignalException(ReservedInstruction) endif 
if NotWordValue(GPR[rs]) then UNPREDICTABLE endif
if NotWordValue(GPR[rt]) then UNPREDICTABLE endif
/* recommended implementation: ignore bits 32-63 for DIV, MOD, DIVU, MODU */
DIV, MOD: 
 s1 = signed_word(GPR[rs])
  s2 = signed_word(GPR[rt])
DIVU, MODU: 
  s1 = unsigned_word(GPR[rs])
  s2 = unsigned_word(GPR[rt])
DDIV, DMOD: 
  s1 = signed_doubleword(GPR[rs])
  s2 = signed_doubleword(GPR[rt])
DDIVU, DMODU: 
  s1 = unsigned_doubleword(GPR[rs])
  s2 = unsigned_doubleword(GPR[rt])
DIV, DIVU, DDIV, DDIVU:
  quotient = s1 div s2
MOD, MODU, DMOD, DMODU:
  remainder = s1 mod s2
DIV:  GPR[rd] = sign_extend.32( quotient )
MOD:  GPR[rd] = sign_extend.32( remainder )
DIVU:  GPR[rd] = sign_extend.32( quotient )
MODU:  GPR[rd] = sign_extend.32( remainder )
DDIV:  GPR[rd] = quotient
DMOD:  GPR[rd] = remainder 
DDIVU: GPR[rd] = quotient 
DMODU: GPR[rd] = remainder 
/* end of instruction */
where
   function zero_or_sign_extended.32(val)
      if value63..32 = (value31)32 then return true
      if value63..32 = (0)32 then return true
      return false
   end function

Exceptions:

DIV, MOD, DIVU, MODU: No arithmetic exceptions occur. Division by zero produces an UNPREDICTABLE result.

DDIV, DMOD, DDIVU, DMODU: Reserved Instruction.