Encoding:

COP0

010000

MTTR

01100

rt

rd

rx

u

h

0

0

sel

6

5

5

5

5

1

1

1

3

Format: 

MTTR rt, rd, u, sel, h

MIPS MT

Move to Thread Context

Purpose:

Move to Thread Context

To move the contents of a general register of the current thread into a register within a targeted thread context.

Description: 

TC[VPEControlTargTC][u,rd,sel,h] = GPR[rt]

The contents of the rt register specifieare written into a register of an arbitrary thread context (TC) or virtual processor (VPE).

The target contextto be written is determined by the value of the TargTC fielof the CP0 VPEControl register (see

Section 6.5). The registerto be written within the selected contextis determined by the value in the rd operand register, in conjunction with the u and sel bits of the MTTR instruction.

Restrictions:

The effect on a TC that is not in a Halted state (i.e., TCHalt.H is 0) of an MTTR instruction targeting that TC may be transient and unstable, but MTTRs setting a TCHalt H bit are always effective until overridden by another MTTR.

Processor state following an MTTR instruction modifying a per-VPE CP0 registeris UNPREDICTABLE if a TC other than the one issuing the MTTR is concurrently active on the targeted VPE.

If the target TC is blocked but not halted,then the thread issuing the MTTR instrution may be blocked indefinitel.

Thisis dueto thetarget TC waiting on an externaleventthat may never happen.Itisrecommended thatthe

TCStatusRNST bit of the target TC be checked before issuing the MtTR instruction.

In any implementation with Floating-Point-Unit, if TCStatusTFR is set so the effective FPR width matches the GPR width, a MFTR instruction targetting one of the FPRs with h=1 will cause UNPREDICTABLE results.

Operation: 

if VPEConf0MVP = 0 and ( TC[VPEControlTargTC].TCBindCurVPE != TCBindCurVPE ) then
   NOOP
else if VPEControlTargTC > MVPConf0PTC then
   NOOP
else
if h = 1 then
      topbit = 63
      bottombit = 32
   else
      topbit = 31
      bottombit = 0
   endif
   if u = 0 then
TC[VPEControlTargTC].CPR[0,rd,sel]topbit..bottombit = GPR[rt]
   else
      case sel
         0: TC[VPEControlTargTC].GPR[rd] = GPR[rt]
         1: case rd
             0: TC[VPEControlTargTC].Lo = GPR[rt]
             1: TC[VPEControlTargTC].Hi = GPR[rt]
             2: TC[VPEControlTargTC].ACX = GPR[rt]
             4: TC[VPEControlTargTC].DSPLo[1] = GPR[rt]
             5: TC[VPEControlTargTC].DSPHi[1] = GPR[rt]
             6: TC[VPEControlTargTC].DSPACX[1] = GPR[rt]
             8: TC[VPEControlTargTC].DSPLo[2] = GPR[rt]
             9: TC[VPEControlTargTC].DSPHi[2] = GPR[rt]
             10:TC[VPEControlTargTC].DSPACX[2] = GPR[rt]
             12:TC[VPEControlTargTC].DSPLo[3] = GPR[rt]
             13:TC[VPEControlTargTC].DSPHi[3] = GPR[rt]
             14:TC[VPEControlTargTC].DSPACX[3] = GPR[rt]
             16:TC[VPEControlTargTC].DSPControl = GPR[rt]
             otherwise: UNPREDICTABLE
         2: if ( ( ConfigAT = 0 and StatusFR = 0) or
                    ( ConfigAT = 1 or ConfigAT = 2) )
                   // GPR and FPR widths match
                   if (h = 0)
                       TC[VPEControlTargTC].FPR[rd] = GPR[rt]
                   else
                       UNPREDICTABLE
                   endif
                elseif (ConfigAT = 0 and StatusFR = 1)
                   // 32-bit GPRs and 64-bit FPRs
                   TC[VPEControlTargTC].FPR[rd]topbit..bottombit = GPR[rt]
                endif
         3: TC[VPEControlTargTC].FPCR[rd] = GPR[rt]
         4: TC[VPEControlTargTC].CP2CPR[rx||rd]topbit..bottombit = GPR[rt]
         5: TC[VPEControlTargTC].CP2CCR[rx||rd]topbit..bottombit = GPR[rt]
         otherwise: UNPREDICTABLE
endif
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction