|
JAL 000011 |
instr_index |
|
6 |
26 |
JAL target |
MIPS32 |
Jump and Link |
Jump and Link
To execute a procedure call within the current 256MB-aligned region.
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call.
This is a PC-region branch (not PC-relative); the effective target address is in the "current" 256MB-aligned region.
The low 28 bits of the target address is the instr_index field shifted left 2bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).
Jump to the effective target address. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs
include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 implementations are required to signal a Reserved Instruction exception.
I: GPR[31] = PC + 8 I+1: PC = PCGPRLEN-1..28 || instr_index || 02
None
Forming the branch target address by catenating PC and index bits rather than adding a signed offset to the PC is an advantage if all program code addresses fit into a 256MB region aligned on a 256MB boundary. It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset.
This definition creates the following boundary case: When the branch instruction is in the last word of a 256MB region, it can branch only to the following 256MB region containing the branch delay slot.
The Jump-and-Link instruction has been deprecated in Release 6. Use BALC instead.