COP1 010001 |
fmt |
0 00000 |
fs |
fd |
ABS 000101 |
6 |
5 |
5 |
5 |
5 |
6 |
ABS.fmt |
Floating Point Absolute Value | |
ABS.S fd, fs |
MIPS32 |
Floating Point Absolute Value |
ABS.D fd, fs |
MIPS32 |
Floating Point Absolute Value |
ABS.PS fd, fs |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Absolute Value |
Floating Point Absolute Value
FPR[fd] = abs(FPR[fs])
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt.
ABS.PS takes the absolute value of the two values in FPR fs independently, and ORs together any generated exceptions.
The Cause bits are ORed into the Flag bits if no exception is taken.
If FIRHas2008=0 or FCSRABS2008=0 then this operation is arithmetic. For this case, any NaN operand signals invalid operation.
If FCSRABS2008=1 then this operation is non-arithmetic. For this case, both regular floating point numbers and NAN values are treated alike, only the sign bit is affected by this instruction. No IEEE exception can be generated for this case, and the FCSRCause and FCSRFlags fields are not modified.
The fields fs and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
The result of ABS.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model.
ABS.PS is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
ABS.PS has been removed in Release 6.
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Coprocessor Unusable, Reserved Instruction
Unimplemented Operation, Invalid Operation