MIPS64 pre-Release 6
SPECIAL2 011100 |
rs |
rt |
rd |
0 00000 |
DCLZ 100100 |
6 |
5 |
5 |
5 |
5 |
6 |
MIPS64 Release 6
SPECIAL 000000 |
rs |
0 00000 |
rd |
00001 |
DCLZ 010010 |
6 |
5 |
5 |
5 |
5 |
6 |
DCLZ rd, rs |
MIPS64 |
Count Leading Zeros in Doubleword |
Count Leading Zeros in Doubleword
To count the number of leading zeros in a doubleword
GPR[rd] = count_leading_zeros GPR[rs]
The 64-bit word in GPR rs is scanned from most significant to least significant bit. The number of leading zeros is counted and the result is written to GPR rd. If no bits were set in GPR rs, the result written to GPR rd is 64.
Pre-Release 6: To be compliant with the MIPS32 and MIPS64 Architecture, software must place the same GPR number in both the rt and rd fields of the instruction. The operation of the instruction is UNPREDICTABLE if the rt and
rd fields of the instruction contain different values. Release 6's new instruction encoding does not contain an rt field.
Release 6 implementations are required to signal a Reserved Instruction exception if the rt field is nonzero.
This instruction has been recoded for Release 6.
temp = 64 for i in 63.. 0 if GPR[rs]i = 1 then temp = 63 - i break endif endfor GPR[rd] = temp
None