Encoding:

Format:

NMADD.fmt 

NMADD.S fd, fr, fs, ft

NMADD.D fd, fr, fs, ft

NMADD.PS fd, fr, fs, ft 

Purpose:

Floating Point Negative Multiply Add

To negate a combined multiply-then-add of FP values.

Description:

 FPR[fd] = - ((FPR[fs] x FPR[ft]) + FPR[fr])

The value in FPR fs is multiplied by the value in FPR ft to produce an intermediate product. The intermediate product is rounded according to the current rounding mode in FCSR. The value in FPR fr is added to the product.

The result sum is calculated to infinite precision, rounded according to the current rounding mode in FCSR, negated by changing the sign bit, and placed into FPR fd. The operands and result are values in format fmt. The results and flags are as if separate floating-point multiply and add and negate instructions were executed.

NMADD.PS applies the operation to the upper and lower halves of FPR fr, FPR fs, and FPR ft independently, and

ORs together any generated exceptional conditions.

The Cause bits are ORed into the Flag bits if no exception is taken.

Restrictions:

The fields fr, fs, ft, and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is

UNPREDICTABLE.

The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.

The result of NMADD.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.

Availability and Compatibility:

This instruction has been removed in Release 6.

NMADD.S and NMADD.D: Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32

Release 1. Required by MIPS32 Release 2 and subsequent versions of MIPS32. When required, these instructions are to be implemented if an FPU is present, either in a 32-bit or 64-bit FPU or in a 32-bit or 64-bit FP Register Mode

(FIR_F64=0 or 1, Status_FR=0 or 1).

Operation:

vfr = ValueFPR(fr, fmt)
vfs = ValueFPR(fs, fmt)
vft = ValueFPR(ft, fmt)
StoreFPR(fd, fmt, -(vfr +fmt (vfs xfmt vft)))

Exceptions:

Coprocessor Unusable, Reserved Instruction

Floating Point Exceptions:

Inexact, Unimplemented Operation, Invalid Operation, Overflow, Underflow