Encoding:

Format:

B{LE,GE,GT,LT,EQ,NE}ZALC 

BLEZALC rt, offset

BGEZALC rt, offset

BGTZALC rt, offset

BLTZALC rt, offset

BEQZALC rt, offset

BNEZALC rt, offset

Purpose:

Compact Zero-Compare and Branch-and-Link Instructions

BLEZALC: Compact branch-and-link if GPR rt is less than or equal to zero

BGEZALC: Compact branch-and-link if GPR rt is greater than or equal to zero

BGTZALC: Compact branch-and-link if GPR rt is greater than zero

BLTZALC: Compact branch-and-link if GPR rt is less than to zero

BEQZALC: Compact branch-and-link if GPR rt is equal to zero

BNEZALC: Compact branch-and-link if GPR rt is not equal to zero

Description:

if condition(GPR[rt]) then procedure_call branch (no delay slot)

The condition is evaluated. If the condition is true, the branch is taken.

Places the return address link in GPR 31. The return link is the address of the instruction immediately following the branch, where execution continues after a procedure call.

The return address link is unconditionally updated.

A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.

BLEZALC: the condition is true if and only if GPR rt is less than or equal to zero.

BGEZALC: the condition is true if and only if GPR rt is greater than or equal to zero.

BLTZALC: the condition is true if and only if GPR rt is less than zero.

BGTZALC: the condition is true if and only if GPR rt is greater than zero.

BEQZALC: the condition is true if and only if GPR rt is equal to zero.

BNEZALC: the condition is true if and only if GPR rt is not equal to zero.

Compact branches do not have delay slots. The instruction after a compact branch is only executed if the branch is not taken.

Restrictions:

Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs

include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.

If a control transfer instruction (CTI) is executed in the forbidden slot of a compact branch, Release 6 implementations are required to signal a Reserved Instruction exception, but only when the branch is not taken.

Branch-and-link Restartability: GPR 31 must not be used for the source registers, because such an instruction does

not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot or forbidden slot.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

• BEQZALC reuses the opcode assigned to pre-Release 6 ADDI.

• BNEZALC reuses the opcode assigned to pre-Release 6 MIPS64 DADDI.

These instructions occupy primary opcode spaces originally allocated to other instructions. BLEZALC and

BGEZALC have the same primary opcode as BLEZ, and are distinguished by rs and rt register numbers. Similarly,

BGTZALC and BLTZALC have the same primary opcode as BGTZ, and are distinguished by register fields.

BEQZALC and BNEZALC reuse the primary opcodes ADDI and DADDI.

Exceptions:

None

Operation:

GPR[31] = PC+4
target_offset = sign_extend( offset || 02 )
BLTZALC: cond = GPR[rt] < 0
BLEZALC: cond = GPR[rt] <= 0
BGEZALC: cond = GPR[rt] >= 0
BGTZALC: cond = GPR[rt] > 0
BEQZALC: cond = GPR[rt] = 0
BNEZALC: cond = GPR[rt] != 0
if cond then
  PC = ( PC+4+ sign_extend( target_offset ) )
endif

Programming Notes:

Software that performs incomplete instruction decode may incorrectly decode these new instructions, because of their very tight encoding. For example, a disassembler might look only at the primary opcode field, instruction bits 31-26, to decode BLEZL without checking that the "rt" field is zero. Such software violated the pre-Release 6 architecture specification.

With the 16-bit offset shifted left 2 bits and sign extended, the conditional branch range is ± 128 KBytes. Other instructions such as pre-Release 6 JAL and JALR, or Release 6 JIALC and BALC have larger ranges. In particular,

BALC, with a 26-bit offset shifted by 2 bits, has a 28-bit range, ± 128 MBytes. Code sequences using AUIPC, DAHI,

DATI, and JIALC allow still greater PC-relative range.