COP1 010001 |
fmt |
rt |
fs |
fd |
MOVZ 010010 |
6 |
5 |
5 |
5 |
5 |
6 |
MOVZ.fmt |
Floating Point Move Conditional on Zero | |
MOVZ.S fd, fs, rt |
MIPS32, removed in Release 6 |
Floating Point Move Conditional on Zero |
MOVZ.D fd, fs, rt |
MIPS32, removed in Release 6 |
Floating Point Move Conditional on Zero |
MOVZ.PS fd, fs, rt |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Move Conditional on Zero |
Floating Point Move Conditional on Zero
To test a GPR then conditionally move an FP value.
if GPR[rt] = 0 then FPR[fd] = FPR[fs]
If the value in GPR rt is equal to zero then the value in FPR fs is placed in FPR fd. The source and destination are values in format fmt.
If GPR rt is not zero, then FPR fs is not copied and FPR fd contains its previous value in format fmt. If fd did not contain a value either in format fmt or previously unused data from a load or move-to operation that could be interpreted in format fmt, then the value of fd becomes UNPREDICTABLE.
The move is non-arithmetic; it causes no IEEE 754 exceptions, and the FCSRCause and FCSRFlags fields are not modified.
The fields fs and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
The result of MOVZ.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model.
It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
This instruction has been removed in Release 6 and has been replaced by the 'SELEQZ fmt' instruction. Refer to the
SELEQZ.fmt instruction in this manual for more information. Release 6 does not support Paired Single (PS).
if GPR[rt] = 0 then StoreFPR(fd, fmt, ValueFPR(fs, fmt)) else StoreFPR(fd, fmt, ValueFPR(fd, fmt)) endif
Coprocessor Unusable, Reserved Instruction
Unimplemented Operation