LDR 011011 |
base |
rt |
offset |
6 |
5 |
5 |
16 |
LDR rt, offset(base) |
MIPS64, removed in Release 6 |
Load Doubleword Right |
Load Doubleword Right
To load the least-significant part of a doubleword from an unaligned memory address
GPR[rt] = GPR[rt] MERGE memory[GPR[base] + offset]
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 8 consecutive bytes forming a doubleword (DW) in memory, starting at an arbitrary byte boundary.
A part of DW, the most-significant 1 to 8 bytes, is in the aligned doubleword containing EffAddr. This part of DW is loaded appropriately into the most-significant (left) part of GPR rt, leaving the remainder of GPR rt unchanged.
This instruction has been removed in Release 6.
Release 6 removes the load/store-left/right family of instructions, and requires the system to support misaligned memory accesses.
vAddr = sign_extend(offset) + GPR[base] (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD) pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor ReverseEndian3) if BigEndianMem = 1 then pAddr = pAddrPSIZE-1..3 || 03 endif byte = vAddr2..0 xor BigEndianCPU3 memdoubleword = LoadMemory (CCA, byte, pAddr, vAddr, DATA) GPR[rt] = GPR[rt]63..64-8*byte || memdoublworde63..8*byte
TLB Refill, TLB Invalid, Bus Error, Address Error, Reserved Instruction, Watch