Encoding:

MSA

011110

000

df

wt

ws

wd

3R

001111

6

3

2

5

5

5

6

Format: 

CEQ.df

Vector Compare Equal

CEQ.B wd,ws,wt

MSA

Vector Compare Equal

CEQ.H wd,ws,wt

MSA

Vector Compare Equal

CEQ.W wd,ws,wt

MSA

Vector Compare Equal

CEQ.D wd,ws,wt

MSA

Vector Compare Equal

Purpose:

Vector Compare Equal

Vector to vector compare for equality; if true all destination bits are set, otherwise clear.

Description: 

wd[i] = (ws[i] = wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt elements are equal, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation: 

CEQ.B:
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i = WR[wt]8i+7..8i
      WR[wd]8i+7..8i = c8
   endfor
CEQ.H:
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i = WR[wt]16i+15..16i
      WR[wd]16i+15..16i = c16
   endfor
CEQ.W:
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i = WR[wt]32i+31..32i
      WR[wd]32i+31..32i = c32
   endfor
CEQ.D:
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i = WR[wt]64i+63..64i
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.