REGIMM 000001 |
0 |
BPOSGE32 11100 |
offset |
6 |
5 |
5 |
16 |
BPOSGE32 offset |
MIPSDSP |
Branch on Greater Than or Equal To Value 32 inDSPControl Pos Field |
Branch on Greater Than or Equal To Value 32 inDSPControl Pos Field
Perform a PC-relative branch if the value of the pos field in the DSPControl register is greater than or equal to 32.
if (DSPControlpos:6..0 >= 32) then goto PC+offset
First, the offset argument is left-shifted by two bits to form an 18-bit signed integer value. This value is added to the address of the instruction immediately following the branch to form a target branch address. Then, if the value of the pos field of the DSPControl register is greater than or equal to 32, the branch is taken and execution begins from the target address after the instruction in the branch delay slot has been executed.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI), specifically a branch, jump, NAL (Release 6), ERET, ERETNC (Release 5), DERET, WAIT, or PAUSE (Release 2) instruction is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 implementations are required to a signal a Reserved Instruction Exception.
Availability:
None.
I: se_offsetGPRLEN..0 = ( offset15 )GPRLEN-18 || offset15..0 || 02 branch_condition = ( DSPControlpos:6..0 >= 32 ? 1 : 0 ) I+1: if ( branch_condition = 1 ) then PCGPRLEN..0 = PCGPRLEN..0 + se_offsetGPRLEN..0 endif
Reserved Instruction, DSP Disabled
With the 18-bit signed instruction offset, the conditional branch range is ±128 Kbytes. Use jump (J) or jump register
(JR) instructions to branch to addresses outside of this range.