COP1 010001 |
fmt |
0 00000 |
fs |
fd |
NEG 000111 |
6 |
5 |
5 |
5 |
5 |
6 |
NEG.fmt |
Floating Point Negate | |
NEG.S fd, fs |
MIPS32 |
Floating Point Negate |
NEG.D fd, fs |
MIPS32 |
Floating Point Negate |
NEG.PS fd, fs |
MIPS64, MIPS32 Release 2, removed in Release 6 |
Floating Point Negate |
Floating Point Negate
To negate an FP value.
FPR[fd] = -FPR[fs]
The value in FPR fs is negated and placed into FPR fd. The value is negated by changing the sign bit value. The operand and result are values in format fmt. NEG.PS negates the upper and lower halves of FPR fs independently, and ORs together any generated exceptional conditions.
If FIRHas2008=0 or FCSRABS2008=0 then this operation is arithmetic. For this case, any NaN operand signals invalid operation.
If FCSRABS2008=1 then this operation is non-arithmetic. For this case, both regular floating point numbers and NAN values are treated alike, only the sign bit is affected by this instruction. No IEEE 754 exception can be generated for this case, and the FCSRCause and FCSRFlags fields are not modified.
The fields fs and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPREDICTABLE. The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand FPR becomes UNPREDICTABLE.
The result of NEG.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
NEG.PS has been removed in Release 6.
StoreFPR(fd, fmt, Negate(ValueFPR(fs, fmt)))
Coprocessor Unusable, Reserved Instruction
Unimplemented Operation, Invalid Operation