COP0 010000 |
MFMC0 01011 |
rt |
1 00001 |
15 01111 |
sc 1 |
0 00 |
1 001 |
6 |
5 |
5 |
5 |
5 |
1 |
2 |
3 |
EMT rt |
MIPS MT |
Enable Multi-Threaded Execution |
To return the previous value of the VPEControl register (see Section 6.5) and to enable multi-threaded execution. If
EMT is specifie without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.
GPR[rt] = VPEControl; VPEControlTE = 1
The current value ofthe VPEControlregisteris loaded into generalregister rt. The Threads Enable (TE) bitin the
VPEControl register is then set, allowing multiple instruction streams to execute concurrently.
If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.
In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.
This operation specificatiois for the general multi-threading enable/disable operation, with the sc (set/clear) fielas a variable. The individual instructions EMT and DMT have a specific alue for the sc field
data = VPEControl GPR[rt] = data VPEControlTE = sc
Coprocessor Unusable
Reserved Instruction (Implementations that do not include the MT Module)
The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, setting the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the EMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.
If an EMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the EMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.