Encoding:

Format:

B<cond>C rs, rt, offset

BEQC rs, rt, offset

BNEC rs, rt, offset

BLTC rs, rt, offset

BGEC rs, rt, offset

BLTUC rs, rt, offset

BGEUC rs, rt, offset

BGTC  rt, rs, offset

BLEC  rt, rs, offset

BGTUC rt, rs, offset

BLEUC rt, rs, offset

BLTZC rt, offset

BLEZC rt, offset 

BGEZC rt, offset

BGTZC rt, offset 

BEQZC rs, offset 

BNEZC rs, offset 

Purpose:

Compact Compare-and-Branch Instructions

Description:

 if condition(GPR[rs] and/or GPR[rt]) then compact branch (no delay slot)

The condition is evaluated. If the condition is true, the branch is taken.

An 18/23-bit signed offset (the 16/21-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.

The offset is 16 bits for most compact branches, including BLTC, BLEC, BGEC, BGTC, BNEQC, BNEC, BLTUC,

BLEUC, BGEUC, BGTC, BLTZC, BLEZC, BGEZC, BGTZC. The offset is 21 bits for BEQZC and BNEZC.

Compact branches have no delay slot: the instruction after the branch is NOT executed if the branch is taken.

The conditions are as follows:

Equal/Not-equal register-register compare-and-branch with 16-bit offset:

BEQC: Compact branch if GPRs are equal

BNEC: Compact branch if GPRs are not equal

Signed register-register compare and branch with 16-bit offset:

BLTC: Compact branch if GPR rs is less than GPR rt

BGEC: Compact branch if GPR rs is greater than or equal to GPR rt

Unsigned register-register compare and branch with 16-bit offset:

BLTUC: Compact branch if GPR rs is less than GPR rt, unsigned

BGEUC: Compact branch if GPR rs is greater than or equal to GPR rt, unsigned

Assembly Idioms with Operands Reversed:

BLEC: Compact branch if GPR rt is less than or equal to GPR rs (alias for BGEC)

BGTC: Compact branch if GPR rt is greater than GPR rs (alias for BLTC)

BLEUC: Compact branch if GPR rt is less than or equal to GPR rt, unsigned (alias for BGEUC)

BGTUC: Compact branch if GPR rt is greater than GPR rs, unsigned (alias for BLTUC)

Compare register to zero and branch with 16-bit offset:

BLTZC: Compact branch if GPR rt is less than zero

BLEZC: Compact branch if GPR rt is less than or equal to zero

BGEZC: Compact branch if GPR rt is greater than or equal to zero

BGTZC: Compact branch if GPR rt is greater than zero

Compare register to zero and branch with 21-bit offset:

BEQZC: Compact branch if GPR rs is equal to zero

BNEZC: Compact branch if GPR rs is not equal to zero

Restrictions:

Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs

include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.

If a control transfer instruction (CTI) is placed in the forbidden slot of a compact branch, Release 6 implementations are required to signal a Reserved Instruction exception, but only when the branch is not taken.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

• BEQZC reuses the opcode assigned to pre-Release 6 LDC2.

• BNEZC reuses the opcode assigned to pre-Release 6 SDC2.

• BEQC reuses the opcode assigned to pre-Release 6 ADDI.

• BNEC reuses the opcode assigned to pre-Release 6 MIPD64 DADDI.

Exceptions:

None

Operation:

target_offset = sign_extend( offset || 02 )
/* Register-register compare and branch, 16 bit offset: */
/* Equal / Not-Equal */
BEQC: cond = GPR[rs] = GPR[rt]
BNEC: cond = GPR[rs] != GPR[rt]
/* Signed */
BLTC: cond = GPR[rs] < GPR[rt]
BGEC: cond = GPR[rs] >= GPR[rt]
/* Unsigned: */
BLTUC: cond = unsigned(GPR[rs]) < unsigned(GPR[rt])
BGEUC: cond = unsigned(GPR[rs]) >= unsigned(GPR[rt])
/* Compare register to zero, small offset: */
BLTZC: cond = GPR[rt] < 0
BLEZC: cond = GPR[rt] <= 0
BGEZC: cond = GPR[rt] >= 0
BGTZC: cond = GPR[rt] > 0
/* Compare register to zero, large offset: */
BEQZC: cond = GPR[rs] = 0
BNEZC: cond = GPR[rs] != 0
if cond then
  PC = ( PC+4+ sign_extend( offset ) )
end if

Programming Notes:

Legacy software that performs incomplete instruction decode may incorrectly decode these new instructions, because of their very tight encoding. For example, a disassembler that looks only at the primary opcode field (instruction bits

31-26) to decode BLEZL without checking that the "rt" field is zero violates the pre-Release 6 architecture specification. Complete instruction decode allows reuse of pre-Release 6 BLEZL opcode for Release 6 conditional branches.