Encoding:

Format:

MUL MUH MULU MUHU DMUL DMUH DMULU DMUHU 

MUL rd,rs,rt

MUH rd,rs,rt

MULU rd,rs,rt

MUHU rd,rs,rt

DMUL rd,rs,rt

DMUH rd,rs,rt

DMULU rd,rs,rt

DMUHU rd,rs,rt

Purpose:

Multiply Integers (with result to GPR)

MUL: Multiply Words Signed, Low Word

MUH: Multiply Words Signed, High Word

MULU: Multiply Words Unsigned, Low Word

MUHU: Multiply Words Unsigned, High Word

DMUL: Multiply Doublewords Signed, Low Doubleword

DMUH: Multiply Doublewords Signed, High Doubleword

DMULU: Multiply Doublewords Unsigned, Low Doubleword

DMUHU: Multiply Doublewords Unsigned, High Doubleword

Description:

MUL:  GPR[rd] = sign_extend.32( lo_word( multiply.signed( GPR[rs] <= GPR[rt] ) ) )
MUH:  GPR[rd] = sign_extend.32( hi_word( multiply.signed( GPR[rs] <= GPR[rt] ) ) )
MULU:  GPR[rd] = sign_extend.32( lo_word( multiply.unsigned( GPR[rs] <= GPR[rt] ) ) )
MUHU:  GPR[rd] = sign_extend.32( hi_word( multiply.unsigned( GPR[rs] <= GPR[rt] ) ) )
DMUL:  GPR[rd] = lo_doubleword( multiply.signed( GPR[rs] <= GPR[rt] ) )
DMUH:  GPR[rd] = hi_doubleword( multiply.signed( GPR[rs] <= GPR[rt] ) )
DMULU: GPR[rd] = lo_doubleword( multiply.unsigned( GPR[rs] <= GPR[rt] ) )
DMUHU: GPR[rd] = hi_doubleword( multiply.unsigned( GPR[rs] <= GPR[rt] ) )

The Release 6 multiply instructions multiply the operands in GPR[rs] and GPR[rd], and place the specified high or low part of the result, of the same width, in GPR[rd].

MUL performs a signed 32-bit integer multiplication, and places the low 32 bits of the result in the destination register.

MUH performs a signed 32-bit integer multiplication, and places the high 32 bits of the result in the destination register.

MULU performs an unsigned 32-bit integer multiplication, and places the low 32 bits of the result in the destination register.

MUHU performs an unsigned 32-bit integer multiplication, and places the high 32 bits of the result in the destination register.

DMUL performs a signed 64-bit integer multiplication, and places the low 64 bits of the result in the destination register.

DMUH performs a signed 64-bit integer multiplication, and places the high 64 bits of the result in the destination register.

DMULU performs an unsigned 64-bit integer multiplication, and places the low 64 bits of the result in the destination register.

DMUHU performs an unsigned 64-bit integer multiplication, and places the high 64 bits of the result in the destination register.

Restrictions:

On a 64-bit CPU, MUH is UNPREDICTABLE if its inputs are not signed extended 32-bit integers.

MUL behaves correctly even if its inputs are not sign extended 32-bit integers. Bits 32-63 of its inputs do not affect the result.

On a 64-bit CPU, MUHU is UNPREDICTABLE if its inputs are not zero or sign extended 32-bit integers.

MULU behaves correctly even if its inputs are not zero or sign extended 32-bit integers. Bits 32-63 of its inputs do not affect the result.

On a 64-bit CPU, the 32-bit multiplications, both signed and unsigned, sign extend the result as if it is a 32-bit signed integer.

DMUL DMUH DMULU DMUHU: Reserved Instruction exception if 64-bit instructions are not enabled.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

Programming Notes:

The low half of the integer multiplication result is identical for signed and unsigned. Nevertheless, there are distinct instructions MUL MULU DMUL DMULU. Implementations may choose to optimize a multiply that produces the low half followed by a multiply that produces the upper half. Programmers are recommended to use matching lower and upper half multiplications.

The Release 6 MUL instruction has the same opcode mnemonic as the pre-Release 6 MUL instruction. The semantics of these instructions are almost identical: both produce the low 32-bits of the 32<=32=64 product; but the pre-Release

6 MUL is unpredictable if its inputs are not properly sign extended 32-bit values on a 64 bit machine, and is defined to render the HI and LO registers unpredictable, whereas the Release 6 version ignores bits 32-63 of the input, and there are no HI/LO registers in Release 6 to be affected.

Operation:

MUH: if NotWordValue(GPR[rs]) then UNPREDICTABLE endif
MUH: if NotWordValue(GPR[rt]) then UNPREDICTABLE endif
MUHU: if NotWordValue(GPR[rs]) then UNPREDICTABLE endif
MUHU: if NotWordValue(GPR[rt]) then UNPREDICTABLE endif
/* recommended implementation: ignore bits 32-63 for MUL, MUH, MULU, MUHU */
MUL, MUH: 
 s1 = signed_word(GPR[rs])
  s2 = signed_word(GPR[rt])
MULU, MUHU: 
  s1 = unsigned_word(GPR[rs])
  s2 = unsigned_word(GPR[rt])
DMUL, DMUH: 
  s1 = signed_doubleword(GPR[rs])
  s2 = signed_doubleword(GPR[rt])
DMULU, DMUHU: 
  s1 = unsigned_doubleword(GPR[rs])
  s2 = unsigned_doubleword(GPR[rt])
product = s1 <= s2    /* product is twice the width of sources */
MUL:  GPR[rd] = sign_extend.32( lo_word( product ) )
MUH:  GPR[rd] = sign_extend.32( hi_word( product ) )
MULU:  GPR[rd] = sign_extend.32( lo_word( product ) )
MUHU:  GPR[rd] = sign_extend.32( hi_word( product ) )
DMUL:  GPR[rd] = lo_doubleword( product )
DMUH:  GPR[rd] = hi_doubleword( product )
DMULU: GPR[rd] = lo_doubleword( product )
DMUHU: GPR[rd] = hi_doubleword( product )

Exceptions:

MUL MUH MULU MUHU: None

DMUL DMUH DMULU DMUHU: Reserved Instruction