Encoding:

Format:

DIVU rs, rt

Purpose:

Divide Unsigned Word

To divide 32-bit unsigned integers

Description:

 (HI, LO) = GPR[rs] / GPR[rt]

The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as unsigned values.

The 32-bit quotient is sign-extended and placed into special register LO and the 32-bit remainder is sign-extended and placed into special register HI.

No arithmetic exception occurs under any circumstances.

Restrictions:

If either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE.

If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE.

Availability and Compatibility:

This instruction has been removed in Release 6.

Operation:

if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then
   UNPREDICTABLE 
endif
q  = (0 || GPR[rs]31..0) div (0 || GPR[rt]31..0)
r  = (0 || GPR[rs]31..0) mod (0 || GPR[rt]31..0)
LO = sign_extend(q31..0)
HI = sign_extend(r31..0)

Exceptions:

None

Programming Notes:

Pre-Release 6 instruction DIV has been removed in Release 6 and has been replaced by DIV and MOD instructions that produce only quotient and remainder, respectively. Refer to the Release 6 introduced 'DIV' and 'MOD' instructions in this manual for more information. This instruction remains current for all release levels lower than Release 6 of the MIPS architecture.

See "Programming Notes" for the DIV instruction.

Historical Perspective:

In MIPS 1 through MIPS III, if either of the two instructions preceding the divide is an MFHI or MFLO, the result of the MFHI or MFLO is UNPREDICTABLE. Reads of the HI or LO special register must be separated from subsequent instructions that write to them by two or more instructions. This restriction was removed in MIPS IV and

MIPS32 and all subsequent levels of the architecture.