Encoding:

Format:

CLT_S.df 

CLT_S.B wd,ws,wt

CLT_S.H wd,ws,wt

CLT_S.W wd,ws,wt

CLT_S.D wd,ws,wt

Purpose:

Vector Compare Signed Less Than

Vector to vector compare for signed less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < wt[i])

Set all bits to 1 i n wd elements if the corresponding ws elements are signed less than wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLT_S.B
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i < WR[wt]8i+7..8i
      WR[wd]8i+7..8i = c8
   endfor
CLT_S.H
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i < WR[wt]16i+15..16i
      WR[wd]16i+15..16i = c16
   endfor
CLT_S.W
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i < WR[wt]32i+31..32i
      WR[wd]32i+31..32i = c32
   endfor
CLT_S.D
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i < WR[wt]64i+63..64i
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.